Physical Design Engineer, Forward Deployed Engineering
openai
Start your Pro trial in 30 seconds (3 days free): you also get the AI match score with your resume.
Role overview
openai is hiring for the Physical Design Engineer, Forward Deployed Engineering role in San Francisco, US. It is full-time with remote work available, Mid-level level, in the Tech sector. It was posted 5/13/2026.
On TalentyGo you can review this job and apply more effectively: Charlie prepares an ATS-optimized resume and a cover letter tailored to "Physical Design Engineer, Forward Deployed Engineering" at openai in about a minute. Before you apply, you can also check how well your profile fits, with a match score based on skills, experience, location and seniority.
- Role
- Physical Design Engineer, Forward Deployed Engineering
- Company
- openai
- Location
- San Francisco, US
- Work mode
- Remote
- Employment
- Full-time
- Seniority
- Mid-level
- Sector
- Tech
- Posted
- 5/13/2026
Description
About the Team
OpenAI’s Forward Deployed Engineering team partners with leading semiconductor companies to deploy production-grade AI systems across the entire chip design lifecycle: design, verification, and physical design. We operate at the intersection of customer delivery and core platform development, embedding deeply with customers to translate frontier model capabilities into systems that materially improve engineering workflows and accelerate innovation.
Our work turns early, high-touch deployments into repeatable solution patterns, reference architectures, and evaluation practices that scale across the semiconductor ecosystem.
About the Role
We are seeking a highly skilled Physical Design Engineer to join our semiconductor-focused Forward Deployed Engineering team. This is a senior IC role that will begin with a strong emphasis on physical design expertise, technical judgment, advisory leverage, and customer credibility, with the expectation that the person will grow into a broader Forward Deployed Engineering role over time.
In the near term, you will serve as the team’s physical design SME across semiconductor deployments: helping FDEs, Product, and Research understand backend implementation workflows, pressure-test AI-assisted solution ideas against real physical design constraints, and raise the quality of our customer-facing technical work. You will help the broader team build fluency in implementation flows, EDA tooling, signoff methodology, and the trade-offs that shape physical design decisions in practice.
Over time, we expect this role to expand beyond SME support into broader FDE ownership: partnering directly with customers, shaping deployment strategy, building and iterating production-grade AI systems, driving technical workstreams, and helping turn high-touch semiconductor deployments into repeatable solutions.
This is a strong fit for someone who brings deep physical design expertise today and is excited to grow into a customer-facing, systems-building, delivery-oriented FDE role.
In this role, you will:
Serve as the physical design SME for semiconductor customer engagements, helping FDE teams understand backend implementation workflows, constraints, and opportunities
Partner with FDEs during customer discovery and scoping to translate ambiguous pain points into clear solution hypotheses, success criteria, and technical plans
Support customer-facing technical conversations as a trusted advisor, engaging credibly with technical leaders
Help shape AI-assisted solutions across physical design workflows, including floorplanning, place and route, clocking, timing closure, congestion, power, physical verification, and signoff
Guide feasibility and integration decisions across the entire chip design lifecycle: design, verification, and physical design
Partner with FDEs and customer SMEs to curate evaluation datasets, golden tasks, rubrics, and acceptance criteria for physical design use cases, ensuring evals reflect real workflows and meaningful success metrics
Build or guide lightweight prototypes, benchmarks, methodology experiments, and internal tools that validate opportunities and accelerate solution development
Educate and mentor the broader FDE team on physical design concepts, implementation flows, EDA tooling, and key trade-offs so the org can engage customers with greater depth and confidence
Surface repeated customer signal to Product and Research to help shape roadmap, model behavior, and platform capabilities for semiconductor use cases
Progressively take on broader FDE responsibilities, including customer discovery, solution architecture, prototype development, production deployment, and ownership of technical workstreams
Minimim Qualifications
BS with 7+ years, MS with 5+ years, or equivalent industry experience in physical design, physical implementation, or backend signoff for complex ASIC or SoC programs
Demonstrated success bringing complex designs through tapeout, with hands-on experience in floorplanning, place and route, CTS, timing closure, power analysis, physical verification, and signoff
Deep familiarity with industry-standard EDA tools and flows for synthesis, PNR, STA, physical verification, equivalence checking, and power analysis
Strong understanding of how physical design intersects with microarchitecture, RTL, verification, design methodology, libraries/PDKs, and system-level PPA trade-offs
Strong communication and collaboration skills, with the ability to translate deep technical trade-offs clearly in customer-facing and cross-functional settings
Comfortable operating as a consultative expert and advisor — unblocking teams, shaping decisions, and raising technical quality without necessarily being the direct implementation owner
Strong scripting and automation skills in Python, Tcl, or similar
Excited to grow beyond domain SME responsibilities into a broader Forward Deployed Engineering role, including hands-on solution building, customer-facing delivery, and ownership of deployment outcomes
Preferred Qualifications
Experience working across multiple semiconductor companies, design environments, or tool stacks, with a point of view shaped by different engineering cultures and methodologies
Experience partnering with external customers, strategic accounts, or design partners in a technical advisory capacity
Experience defining or scaling evaluation workflows, benchmarks, or acceptance criteria
Exposure to adjacent workflows such as design and/or verification
Experience applying AI/LLM systems to semiconductor workflows
Prior experience in solutions engineering, field engineering, customer-facing technical delivery, or consultative technical roles
Compensation Range: $162K - $302K USD
About OpenAI
OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.
We are an equal opportunity employer, and we do not disc
The market for this role in San Francisco
TalentyGo lists 7278 similar roles (815 in San Francisco), 22% remote. Charlie ranks them against your CV, each with a clear score.
Similar jobs
TalentyGo is an aggregator of job postings from public sources. Always verify information directly with the company. Applications go through the original company website; TalentyGo does not manage hiring processes.